XRT72L13 Datasheet, PDF (233/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
)
TX DS3 F-BIT MASK REGISTER - 3 (ADDRESS = 0X38)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FBit Mask[15] FBit Mask[14] FBit Mask[13] FBit Mask[12] FBit Mask[11] FBit Mask[10] FBit Mask[9] FBit Mask[8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7 - 0 F-Bit Mask[15:8]
These "Read/Write" bit-fields allow the user to insert
errors into the thirteenth through twentieth F-bits of a
DS3 M-frame, for test and diagnostic purposes. The
Transmit DS3 Framer automatically performs an XOR
operation on the actual contents of these F-bit fields
to these register bit-fields. Therefore, for every "1"
that exists in these bit-fields, this will result in a
change of state for the corresponding F-bit, prior to
being transmitted to the Far-End Receive DS3 Fram-
er.
If the user wishes to operate the Transmit DS3 Fram-
er in the normal mode (e.g., when no errors are being
injected into these F-bit fields of the outbound DS3
frames), then he/she must ensure that all of these bit-
fields are "0s".
3.3.2.53 TxDS3 F-Bit Mask4 Register
)
TXDS3 F-BIT MASK REGISTER - 4 (ADDRESS = 0X39)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FBit Mask[7] FBit Mask[6] FBit Mask[5] FBit Mask[4] FBit Mask[3] FBit Mask[2] FBit Mask[1] FBit Mask[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7 - 0 F-Bit Mask[7:0]
These "Read/Write" bit-fields allow the user to insert
errors into the last eight F-bits of a DS3 M-frame, for
test and diagnostic purposes. The Transmit DS3
Framer automatically performs an XOR operation on
the actual contents of these F-bit fields to these regis-
ter bit-fields. Therefore, for every "1" that exists in
these bit-fields, this will result in a change of state for
the corresponding F-bit, prior to being transmitted to
the Far-End Receive DS3 Framer.
If the user wishes to operate the Transmit DS3 Fram-
er in the normal mode (e.g., when no errors are being
injected into these F-bit fields of the outbound DS3
3.3.2.54 M12 DS2 # 1 Framer Configuration
Register
3.3.2.56 M12 DS2 # 3 Framer Configuration
Register
3.3.2.57 M12 DS2 # 4 Framer Configuration
Register
3.3.2.58 M12 DS2 # 5 Framer Configuration
Register
3.3.2.59 M12 DS2 # 6 Framer Configuration
Register
3.3.2.60 M12 DS2 # 7 Framer Configuration
Register
3.3.2.55 M12 DS2 # 2 Framer Configuration
Register
3.3.2.61 PMON LCV Event Count Register -
MSB
221