XRT72L13 Datasheet, PDF (147/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
last read of these registers. This register contains the 2.3.2.70 PMON CP-Bit Error Event Count Regis-
LSB (or Lower-Byte) value of this 16 bit expression. ter - MSB
PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
CP-Bit Error Count - High Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON CP-Bit Error Count Register - LSB" (Address
= 0x59) contains a 16-bit representation of the num-
ber of "CP-bit Errors that have been detected by the
Receive DS3 Framer block (within the chip), since the
last read of these registers. This register contains the
MSB (or Upper-Byte) value of this 16 bit expression.
2.3.2.71 PMON CP-Bit Error Event Count Regis-
ter - LSB
PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
CP-Bit Error Count - Low Byte
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON CP-Bit Error Count Register - MSB" (Address
= 0x58) contains a 16-bit representation of the num-
ber of "CP-bit Errors that have been detected by the
Receive DS3 Framer block (within the chip), since the
last read of these registers. This register contains the
MSB (or Upper-Byte) value of this 16 bit expression.
2.3.2.72 PMON DS2 # 1 Framing Bit Error Count
Register
PMON DS2 # 1 FRAMING BIT ERROR COUNT REGISTER (ADDRESS = 0X5A)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
DS2 # 1 Framing-Bit Error Count
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This “Reset-upon Read” register contains an 8-bit
representation of the number of “F” or “M-” bit errors
that have been detected by Receive DS2 Framer # 1
(within the chip), since the last read of this register.
2.3.2.73 PMON DS2 # 2 Framing Bit Error Count
Register
PMON DS2 # 2 FRAMING BIT ERROR COUNT REGISTER (ADDRESS = 0X5B)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
DS2 # 2 Framing-Bit Error Count
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This “Reset-upon Read” register contains an 8-bit
representation of the number of “F” or “M-” bit errors
that have been detected by Receive DS2 Framer # 2
(within the chip), since the last read of this register.
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