XRT72L13 Datasheet, PDF (297/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
• Set Bit 0 (TxLAPD Interrupt Status) within the
“TxDS3 LAPD Status and Interrupt” Register, as
illustrated below.
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Not Used
TxDL Start TxDL Busy
RO
RO
RO
RO
R/W
RO
0
0
0
0
0
0
BIT 1
TxLAPD
Interrupt
Enable
R/W
0
BIT 0
TxLAPD
Interrupt
Status
RUR
1
The purpose of this interrupt is to alert the Microcon-
troller/MIcroprocessor that the “LAPD Transmitter”
has completed its transmission of a given LAPD (or
PMDL) Message, and is now ready to transmit the
next PMDL Message, to the Remote Terminal Equip-
ment.
4.3 THE RECEIVE SECTION OF THE XRT72L13 (DS3
MODE OPERATION)
When the XRT72L13 has been configured to operate
in the DS3 Mode, the Receive Section of the
XRT72L13 consists of the following functional blocks.
• Receive LIU Interface block
• Receive HDLC Controller block
• Receive DS3 Framer block
• Receive Overhead Data Output Interface block
• Receive Payload Data Output Interface block
Figure 91 presents a simple illustration of the Re-
ceive Section of the XRT72L13 Framer IC.
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