XRT72L13 Datasheet, PDF (214/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
This “Read/Write” bit-field permits the user to enable
or disable the “Change in OOF Condition” Interrupt.
Setting this bit-field to “0” disables the “Change in
OOF Condition” Interrupt.
Setting this bit-field to “1” enables the “Change in
OOF Condition” Interrupt.
Bit 0 - Detection of P-Bit Error Interrupt Enable
This “Read/Write” bit-field permits the user to enable
or disable the “Detection of P-Bit Error” Interrupt.
Setting this bit-field to “0” disables the “Detection of
P-Bit Error” Interrupt.
Setting this bit-field to “1” enables the “Detection of P-
Bit Error” Interrupt.
3.3.2.17 RxDS3 Interrupt Status Register
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Detection of
CP-Bit Error
Interrupt
Status
Change in
LOS
Condition
Interrupt
Status
Change in
AIS
Condition
Interrupt
Status
Change in
Idle Pattern
Condition
Interrupt
Status
Change in
FERF
Condition
Interrupt
Status
Change in
AIC State
Interrupt
Status
Change in
OOF
Condition
Interrupt
Status
Detection of
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
Bit 7 - Detection of CP-Bit Error Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not the “Receive DS3 Framer” block has detected a
“CP-Bit Error” in the “inbound” DS3 data stream,
since the last time this register was read.
This bit-field will be “0” if the “Detection of CP-Bit Er-
ror” interrupt has not occured since the last read of
this register.
This bit-field will be “1” if the interrupt has occurred
since the last read of this register.
Bit 6 - Change in LOS (Loss of Signal) Condition
Interrupt Status
This “Reset-upon-Read” bit-field will be set to “1” if
the “Receive DS3 Framer” block has detected a
“Change in LOS” condition, since the last time this
register was read. If the “Change in LOS Condition”
interrupt is enabled, then this bit-field will be asserted
under either of the following conditions.
a. When the Receive DS3 Framer block detects
the occurrence of an LOS condition (e.g., the
occurrence of 180 consecutive “spaces” in the
incoming DS3 data stream), and
b. When the Receive DS3 Framer block detects the
end of an LOS condition (e.g., when the “Receive
DS3 Framer” block detects at least 60 mark pulses
in the last 180 bit periods).
The Microprocessor/Microcontroller can determine
the state of the LOS condition by reading bit 6, within
the “Rx DS3 Configuration and Status” register (Ad-
dress location = 0x10).
NOTE: For more information about the “LOS Condition”
please see Section _.
Bit 5 - Change in AIS (Alarm Indication Signal)
Condition Interrupt Status
This “Reset-upon-Read” bit-field will be set to “1” if
the “Receive DS3 Framer” block has detected a
“Change in AIS” condition, since the last time this reg-
ister was read. If the “Change in AIS Condition” inter-
rupt is enabled, then this bit-field will be asserted un-
der either of the following conditions.
a. When the Receive DS3 Framer block first
detects an AIS condition in the inbound DS3 data
stream.
b. When the Receive DS3 Framer block has
detected the end of an “AIS Condition”.
The Microprocessor/Microcontroller can determine
the state of the AIS condition by reading bit 7, within
the “Rx DS3 Configuration and Status” Register (Ad-
dress location = 0x10).
NOTE: For more information about the “AIS Condition”
please see Section _.
Bit 4 - Change in Idle Pattern Condition Interrupt
Status
This “Reset-upon-Read” bit-field is set to “1” when the
Receive DS3 Framer block detects a “Change in Idle
Condition” in the incoming DS3 data stream. Specifi-
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