XRT72L13 Datasheet, PDF (212/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
M13 device) is currently declaring an “OOF” (Out of
Frame) condition.
If this bit-field is set to “0”, then the “Receive DS3
Framer” block (of the chip) is currently not declaring
the “OOF” condition.
If this bit-field is set to “1”, then the “Receive DS3
Framer block is currently declaring the “OOF” condi-
tion.
NOTE: For more information on the “OOF” and “In-Frame”
Declaration Criteria (for DS3) please see Section _.
Bit 2 - Framing On Parity ON/OFF Select
This “Read/Write” bit-field permits the user to require
that the “Receive DS3 Framer” block include P-Bit
Verification as a condition for declaring itself “In-
Frame”, during “Frame Acquisition”.
This feature also imposes an additional “Frame Main-
tenance” requirement on the “Receive DS3 Framer”
block. In particular, if this additional requirement is
implemented, the “Receive DS3 Framer” block will
perform a frame search if it detects P-bit errors in at
least 2 out of 5 DS3 frames.
Setting this bit-field to “1” imposes this additional re-
quirement.
Conversely, setting this bit-field to “0” configures the
“Receive DS3 Framer” block to waive this require-
ment.
NOTE: For more information on “Framing with Parity”,
please see Section _.
Bit 1 - FSync Algo(rithm) Select
This “Read/Write” bit-field, in conjunction with Bits 0
and 2 of this register, allows the user to completely
define the “Frame Maintenance” criteria of the “Re-
ceive DS3 Framer” block (within the chip). This par-
ticular bit-field permits the user to define the “Frame
Maintenance” criteria, as it applies to F-bits.
Setting this bit-field to “0” configures the “Receive
DS3 Framer” block to declare an “OOF” (Out of
Frame” condition) if it determines that 6 out of the last
16 F-bits are in error.
Setting this bit-field to “1” configures the “Receive
DS3 Framer” block to declare an “OOF” (Out of
Frame” condition) if it determines that 3 out of the last
16 F-bits are in error.
Bit 0 - MSync Algo(rithm) Select
This “Read/Write” bit-field, in conjunction with Bits 1
and 2 of this register, allows the user to completely
define the “Frame Maintenance” criteria of the “Re-
ceive DS3 Framer” block (within the chip). This par-
ticular bit-field permits the user to define the “Frame
Maintenance” criteria, as it applies to M-bits.
Setting this bit-field to “0” configures the “Receive
DS3 Framer” block to ignore the occurrence of M-bit
errors.
Setting this bit-field to “1” configures the “Receive
DS3 Framer” block to declare an “OOF” condition if it
determines that 3 out of 4 M-bits are in error.
3.3.2.15 RxDS3 Status Register
RX DS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used Not Used
Not Used
RxFERF
RxAIC
RxFEBE[2] RxFEBE[1] RxFEBE[0]
R/O
R/W
R/W
R/O
R/O
R/O
R/O
R/O
0
0
0
0
0
0
0
0
Bit 4 - RxFERF (Far-End Receive Failure) Indicator
This “Read-Only” bit-field indicates whether or not the
“Receive DS3 Framer” block (within the XRT72L13
M13 device) is declaring a FERF (Far-End Receive
Failure) condition.
If this bit-field is set to “0”, then the “Receive DS3
Framer” block (of the chip) is currently not declaring
an LOS condition.
Conversely, if this bit-field is set to “1”, then the “Re-
ceive DS3 Framer” block is currently declaring an
LOS condition.
NOTE: For more information how the “Receive DS3 Framer”
block declares a “FERF” condition, please see Section _.
Bit 3 - RxAIC (Application Identification Channel) indi-
cator
This “Read-Only” bit-field reflects the value of the AIC
bit-field, within the incoming DS3 frames, as detected
by the “Receive DS3 Framer” block.
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