XRT72L13 Datasheet, PDF (215/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
cally, the Receive DS3 Framer block will assert this
bit-field under either of the following two conditions.
a. When the Receive DS3 Framer block initially
detects the “Idle Pattern” in the “inbound” DS3 data
stream.
b. When the Receive DS3 Framer block ceases to
detect the “Idle Pattern” in the “inbound” DS3 data
stream.
The Microprocessor/Microcontroller can determine
the state of the “Idle Pattern Condition” by reading bit
5, within the “Rx DS3 Configuration and Status” regis-
ter (Address location = 0x10).
NOTE: For more information about the “Idle Pattern” please
see Section _.
Bit 3 - Change in FERF Condition Interrupt Status
This “Reset-upon-Read” bit-field is set to “1” if the
“Receive DS3 Framer” block (within the XRT72L13
M13 device) has detected a “Change in the FERF”
Condition, since the last time this register was read.
This bit-field will be asserted under either of the fol-
lowing conditions.
a. When the Receive DS3 Framer block first
detects the occurrence of a “FERF” condition in the
“inbound” DS3 data stream (e.g., all X-bits are set
to “0”).
b. When the Receive DS3 Framer block no longer
detects the “FERF” condition in the “inbound” DS3
data stream (e.g., all X-bits are set to “1”).
The Microprocessor/Microcontroller can determine
the state of the of the “FERF” condition by reading bit
4 within the “Rx DS3 Status” register (Address loca-
tion = 0x11).
NOTE: For more information about the “FERF” condition,
please see Section _.
Bit 2 - Change in AIC State Interrupt Status
This “Reset-upon-Read” bit-field is set to “1” if the AIC
bit-field, within the incoming DS3 data stream, has
changed state since the last read of this register.
The Microprocessor/Microcontroller can determine
the state of the “AIC” bit-field by reading bit 3, within
the “Rx DS3 Status” Register (Address location =
0x11).
NOTE: For more information on this interrupt condition,
please see Section _.
Bit 1 - Change in OOF Condition Interrupt Status
The “Reset-upon-Read” bit-field is set to “1” if the
“Receive DS3 Framer” block (within the XRT72L13)
has detected a “Change in the Out-of-Frame” (OOF)
condition, since the last time this register was read.
This bit-field will be asserted under either of the fol-
lowing conditions.
a. When the “Receive DS3 Framer” block has
detected the appropriate condition to declare an
“OOF” condition.
b. When the “Receive DS3 Framer” block has tran-
sitioned from the “OOF” condition (Frame Acquisi-
tion Mode).
The Microprocessor/Microcontroller can detemine the
state of the “OOF” condition by reading bit 4 within
the “Rx DS3 Configuration and Status” Register (Ad-
dress location = 0x10).
NOTE: For more information about the “OOF” condition,
please see Section _.
Bit 0 - Detection of P-Bit Error Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not the “Detection of P-Bit Error” interrupt has oc-
curred since the last read of this register.
This bit-field will be “0” if the “Receive DS3 Framer”
block (within the XRT72L13 M13 device) has not de-
tected a P-bit error since the last read of this register.
Conversely, this bit-field will be “1” if the “Receive
DS3 Framer” block (within the XRT72L13 M13 de-
vice) has detected a P-Bit error since the last read of
this register.
3.3.2.18 RxDS3 Sync Detect Register
RX DS3 SYNC DETECT REGISTER (ADDRESS = 0X14)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
Not Used
Not Used
Reserved
Reserved
Reserved
F
Algorithm
One and
Only One
R/O
R/O
R/O
R/O
R/O
R/O
R/W
R/W
0
0
0
0
0
0
0
0
Bit 1 - F Algorithm
Bit 0 - One and Only One
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