XRT72L13 Datasheet, PDF (317/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
The bit-format of the "Rx DS3 FEAC" register is pre- idated" FEAC code word will be written into the
sented below. It is important to note that the "last val- "shaded" bit-fields below.
RX DS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Not Used RxFEAC [5] RxFEAC [4] RxFEAC [3] RxFEAC [2] RxFEAC [1] RxFEAC [0] ^{Not Used}
RO
RO
RO
RO
RO
RO
RO
RO
0
d5
d4
d3
d2
d1
d0
0
The purpose of generating an interrupt to the µP, up-
on "FEAC Code Word Validation" is to inform the local
µP that the Framer has a "newly received" FEAC
message that needs to be read. The local µP would
read-in this FEAC code word from the Rx DS3 FEAC
Register (Address = 0x16).
FEAC Code Removal
After the 10th transmission of a given FEAC code
word, the remote terminal equipment may proceed to
transmit a different FEAC code word. When the Re-
ceive FEAC processor detects this occurrence, it
must "Remove" the FEAC codeword that is presently
residing in the "Rx DS3 FEAC" Register. The Re-
ceive FEAC Processor will "remove" the existing
FEAC code word when it detects that 3 (or more) out
of the last 10 received FEAC codes are different from
the latest "validated" FEAC code word. The Receive
FEAC Processor will inform the local µP/µC of this
"removal" event by generating a "Rx FEAC Removal"
interrupt, and asserting the "RxFEAC Remove Inter-
rupt Status" bit in the Rx DS3 Interrupt Enable/Status
Register, as depicted below.
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
Not Used
BIT 6
Not Used
BIT 5
Not Used
BIT 4
FEAC
Valid
RO
RO
RO
RO
X
X
X
0
Additionally, the Receive FEAC processor will also
denote the "removal" event by setting the "FEAC Val-
id" bit-field (Bit 4), within the "Rx DS3 FEAC Interrupt
Enable/Status" Register to "0", as depicted above.
The description of Bits 0 through 3 within this register,
all support Interrupt Processing, and will therefore be
BIT 3
BIT2
BIT 1
BIT 0
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
R/W
RUR
R/W
RUR
1
1
X
0
presented in Section 3.3.6. Figure 103 presents a
flow diagram depicting how the Receive FEAC Pro-
cessor functions.
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