XRT72L13 Datasheet, PDF (109/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
2.3.2.21 RxDS3 FEAC Interrupt Enable/Status
Register
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
R/O
0
BIT 6
Not Used
R/O
0
BIT 5
R/O
0
BIT 4
FEAC Valid
R/O
0
BIT 3
RxFEAC
Remove
Interrupt
Enable
R/W
0
BIT 2
RxFEAC
Remove
Interrupt
Status
RUR
0
BIT 1
RxFEAC
Valid
Interrupt
Enable
R/W
0
BIT 0
RxFEAC
Valid
Interrupt
Status
RUR
0
Bit 4 - FEAC Valid
This "Read Only" bit is set to "1" when an incoming
FEAC Message Code has been validated by the Re-
ceive DS3 Framer. This bit is cleared to "0" when the
FEAC code is removed.
NOTE: For more information on the role of this bit-field and
the Receive FEAC Processor, please see Section _.
Bit 3 - RxFEAC Remove Interrupt Enable
This "Read/Write" bit-field allows the user to enable/
disable the "RxFEAC Removal" interrupt. Writing a
"1" to this bit enables this interrupt. Likewise, writing
a "0" to this bit-field disables this interrupt.
NOTE: For more information on the role of this bit-field and
the Receive FEAC Processor, please see Section _.
Bit 2 - RxFEAC Remove Interrupt Status
A "1" in this "Read Only" bit-field indicates that the
last "validated" FEAC Message has now been re-
moved by the Receive FEAC Processor. The Re-
ceive FEAC Processor will remove a validated FEAC
message if 3 out of the last 10 received FEAC mes-
sages differ from the latest valid FEAC Message.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section _.
Bit 1 - RxFEAC Valid Interrupt Enable
This "Read/Write" bit-field allows the user to enable/
disable the "Rx FEAC Valid" interrupt. Writing a "1" to
this bit-field enables this interrupt. Whereas, writing a
"0" disables this interrupt. The value of this bit-field is
"0" following power up or reset.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section _.
Bit 0 - RxFEAC Valid Interrupt Status
A "1" in this "Read Only" bit-field indicates that a new-
ly received FEAC Message has been validated by the
Receive FEAC Processor.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section _.
2.3.2.22 RxDS3 LAPD Control Register
RXDS3 LAPD CONTROL REGISTER (ADDRESS = 0X18)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
RxLAPD
Any
RO
0
BIT 2
RxLAPD
Enable
R/W
0
BIT 1
RxLAPD
Interrupt
Enable
R/W
0
BIT 0
RxLAPD
Interrupt
Status
RUR
0
Bit 3 RxLAPD Any
To be provided in the next revision.
Bit 2 RxLAPD Enable
This "Read/Write" bit-field allows the user to enable
or disable the LAPD Receiver. The LAPD Receiver
MUST be enabled before it can begin to receive and
process any LAPD Message frames from the incom-
ing DS3 data stream.
Writing a "0" to this bit-field disables the LAPD Re-
ceiver (the default condition). Writing a "1" to this bit-
field enables the LAPD Receiver.
Bit 1 RxLAPD (Message Frame Reception Com-
plete) Interrupt Enable
This "Read/Write" bit-field allows the user to enable
or disable the "LAPD Message Frame Reception
Complete" interrupt. If this interrupt is enabled, then
the UNI will generate this interrupt to the local µP,
once the last bit of a LAPD Message frame has been
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