XRT72L13 Datasheet, PDF (349/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
Servicing the “Detection of CP-Bit Error” Inter-
rupt
Whenever the XRT72L13 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the “Interrupt Request” output pin
(INT*) by driving it “HIGH”.
• It will set Bit 7 (CP-Bit Error Interrupt Status) within
the “Rx DS3 Interrupt Status” Register, to “1”, as
indicated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
1
0
0
0
0
0
0
1
Whenever the “Terminal Equipment” encounters the
“Detection of CP-bit Error” Interrupt, it should do the
following.
• It should read contents of “PMON Frame CP-Bit
Error Count” Register (located at 0x72 and 0x73),
in order to determine the number of CP-bit errors
recently received.
4.3.6.2.9 The “Receive FEAC Message - Valida-
tion” Interrupt
If the “Receive FEAC Message - Validation” Interrupt
is enabled, then the XRT72L13 Framer IC will gener-
ate an interrupt any time the “Receive FEAC Proces-
sor” validates a new FEAC (Far-End Alarm & Control)
Message.
In partcular, the “Receive FEAC Processor” will vali-
date a FEAC Message, it that same FEAC Message
has been received in 8 of the last 10 FEAC Message
receptions.
Enabling/Disabling the “Receive FEAC Message -
Validation” Interrupt
The user can enable or disable the “Receive FEAC
Message - Validation” Interrupt, by writing the appro-
priate data into Bit 1 (RxFEAC Valid Interrupt Enable)
within the “RxDS3 FEAC Interrupt Enable/Status”
Register, as indicated below.
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FEAC Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
RO
RO
RO
RO
R/W
RUR
R/W
RUR
0
0
0
0
0
0
X
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the “Receive FEAC Message - Valida-
tion” Interrupt.
Whenever the XRT72L13 Framer IC generates this
interrupt, it will do the following.
• It will assert the “Interrupt Request” output pin
(INT*) by driving it “LOW”.
• It will set Bit 0 (RxFEAC Valid Interrupt Status),
within the “RxDS3 FEAC Interrupt Enable/Status”
Register to “1”, as indicated below.
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