C8051F54X_14 Datasheet, PDF (97/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 12.2. SFRPAGE: SFR Page
Bit
7
6
5
4
3
2
1
0
Name
SFRPAGE[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA7; SFR Page = All Pages
Bit
Name
Function
7:0 SFRPAGE[7:0] SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
When enabled in the SFR Page Control Register (SFR0CN), the C8051 core will
automatically switch to the SFR Page that contains the SFRs of the correspond-
ing peripheral/function that caused the interrupt, and return to the previous SFR
page upon return from interrupt (unless SFR Stack was altered before a return-
ing from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and
push/pop events of this stack are caused by interrupts (and not by reading/writ-
ing to the SFRPAGE register)
Rev. 1.1
97