C8051F54X_14 Datasheet, PDF (23/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

4. Package Specifications
4.1. QFP-32 Package Specifications
C8051F54x
Figure 4.1. QFP-32 Package Drawing
Table 4.1. QFP-32 Package Dimensions
Dimension Min
Typ
Max
Dimension Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
—
0.20
D
9.00 BSC.
D1
7.00 BSC.
e
0.80 BSC.
E
9.00 BSC.
E1
7.00 BSC.
L
0.45
0.60
0.75
aaa
0.20
bbb
0.20
ccc
0.10
ddd
0.20

0°
3.5°
7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.1
23