C8051F54X_14 Datasheet, PDF (256/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn ^ENB
1
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
x 00
0x
PCA0CPLn PCA0CPHn
PCA Interrupt
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
Enable
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Match
Toggle
0
1
TOGn
0 _{CEXn Crossbar}
1
Figure 24.6. PCA High-Speed Output Mode Diagram
Port I/O
24.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 24.1.
F_CEXn
=
---------------^F----^P---^C----^A----------------
2  PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 24.1. Square Wave Frequency Output
Where F_PCA is the frequency of the clock selected by the CPS[2:0] bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
256
Rev. 1.1