C8051F54X_14 Datasheet, PDF (182/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
LIN Register Definition 19.6. LIN0ST: LIN0 Status Register
Bit
7
6
5
4
3
2
1
0
Name ACTIVE IDLTOUT ABORT DTREQ LININT ERROR WAKEUP DONE
Type
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Indirect Address = 0x09
Bit Name
Function
7 ACTIVE LIN Active Indicator Bit.
0: No transmission activity detected on the LIN bus.
1: Transmission activity detected on the LIN bus.
6
IDLT Bus Idle Timeout Bit. (slave mode only)
0: The bus has not been idle for four seconds.
1: No bus activity has been detected for four seconds, but the bus is not yet in Sleep
mode.
5 ABORT Aborted Transmission Bit. (slave mode only)
0: The current transmission has not been interrupted or stopped. This bit is reset to 0
after receiving a SYNCH BREAK that does not interrupt a pending transmission.
1: New SYNCH BREAK detected before the end of the last transmission or the STOP
bit (LIN0CTRL.7) has been set.
4 DTREQ Data Request Bit. (slave mode only)
0: Data identifier has not been received.
1: Data identifier has been received.
3
LININT Interrupt Request Bit.
0: An interrupt is not pending. This bit is cleared by setting RSTINT (LIN0CTRL.3)
1: There is a pending LIN0 interrupt.
2 ERROR Communication Error Bit.
0: No error has been detected. This bit is cleared by setting RSTERR (LIN0CTRL.2)
1: An error has been detected.
1 WAKEUP Wakeup Bit.
0: A wakeup signal is not being transmitted and has not been received.
1: A wakeup signal is being transmitted or has been received
0
DONE Transmission Complete Bit.
0: A transmission is not in progress or has not been started. This bit is cleared at the
start of a transmission.
1: The current transmission is complete.
182
Rev. 1.1