C8051F54X_14 Datasheet, PDF (15/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
C2CK/RST
VREGIN
VDD
GND
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051 Controller
Core (50 MHz)
16 kB Flash Program
Memory
256 Byte RAM
1 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator
(±0.5%)
External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
SPI
I2C
Priority
Crossbar
Decoder
Crossbar Control
Analog Peripherals
Voltage
Reference _VREF
VDD
VREF
12-bit
200ksps
A
M
U
ADC
X
VDD
VREF
P0 – P2
Temp
Sensor
GND
CP0, CP0A ₊
Comparator 0 ^-
CP1, CP1A ₊
Comparator 1 ^-
Figure 1.2. C8051F542/3/6/7 Block Diagram
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1/C2D
Rev. 1.1
15