C8051F54X_14 Datasheet, PDF (160/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.10. P3MASK: Port 3 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
0
0
0
0
0
0
0 P3MASK[0]
Type
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xAF; SFR Page = 0x00
Bit
Name
Function
7:1
Unused Read = 0000000b; Write = Don’t Care.
0 P3MASK[7:0] Port 3 Mask Value.
Selects P3.n pins to be compared to the corresponding bits in P3MAT.
0: P3.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P3.n pin logic value is compared to P3MAT.n.
Note: P3.0 is only available on the 32-pin packages.
SFR Definition 18.11. P3MAT: Port 3 Match Register
Bit
7
6
5
4
3
2
1
0
Name
0
0
0
0
0
0
0
P3MAT[0]
Type
R
R
R
R
R
R
R
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xAE; SFR Page = 0x00
Bit
Name
Function
7:1
Unused Read = 0000000b; Write = Don’t Care.
0
P3MAT[0] Port 3 Match Value.
Match comparison value used on Port 3 for bits in P3MAT which are set to 1.
0: P3.n pin logic value is compared with logic LOW.
1: P3.n pin logic value is compared with logic HIGH.
Note: P3.0 is only available on the 32-pin packages.
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Rev. 1.1