C8051F54X_14 Datasheet, PDF (36/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = 1, GAIN = 0xFC0 = 4032, and the
resulting equation is as follows:
GAIN
=


44----00---39----26-_
+
1



6--1--4--^
=
0.984 + 0.016
=
1.0
The table below equates values in the ADC0GNH, ADC0GNL, and ADC0GNA registers to the equivalent
gain using this equation.
ADC0GNH Value
0xFC (default)
0x7C
0xBC
0x3C
0xFF
0xFF
ADC0GNL Value
0x00 (default)
0x00
0x00
0x00
0xF0
0xF0
GAINADD Value
1 (default)
1
1
1
0
1
GAIN Value
4032 + 64
1984 + 64
3008 + 64
960 + 64
4095 + 0
4096 + 64
Equivalent Gain
1.0 (default)
0.5
0.75
0.25
~1.0
1.016
For any desired gain value, the GAIN registers can be calculated by the following:
GAIN = _gain – GAINADD  _{6--1-4--}  4096
Equation 5.3. Calculating the ADC0GNH and ADC0GNL Values from the Desired Gain
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
When calculating the value of GAIN to load into the ADC0GNH and ADC0GNL registers, the GAINADD bit
can be turned on or off to reach a value closer to the desired gain value.
For example, the initial example in this section requires a gain of 0.44 to convert 5 V full scale to 2.2 V full
scale. Using Equation 5.3:
GAIN
=


0.44
–
GAI
NADD



6--1--4-^{ }
 4096
If GAINADD is set to 1, this makes the equation:
GAIN
=
 ^0.44
–
1



6--1--4-^


 4096
=
0.424  4096
=
1738
=
0x06CA
The actual gain from setting GAINADD to 1 and ADC0GNH and ADC0GNL to 0x6CA is 0.4399. A similar
gain can be achieved if GAINADD is set to 0 with a different value for ADC0GNH and ADC0GNL.
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Rev. 1.1