C8051F54X_14 Datasheet, PDF (33/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
Note: When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Idle
TC TC TC TC
Powered
Down
Power-Up
and Track
TC TC TC TC
AD0PWR
Powered
Down
Powered
Down
Post-Tracking
AD0TM = 01
AD0EN = 1
Dual-Tracking
AD0TM = 11
AD0EN = 1
Idle T C T C T C T C
Track T C T C T C T C
Idle
Track
T = Tracking
C = Converting
Power-Up
and Idle
T C..
Power-Up
and Track
T C..
T C T C T C..
T C T C T C..
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down
Power-Up
and Idle
TC
Powered
Down
Power-Up
and Track
TC
AD0PWR
Powered
Down
Powered
Down
Power-Up
and Idle
T C..
Power-Up
and Track
T C..
Post-Tracking
AD0TM = 01
AD0EN = 1
Dual-Tracking
AD0TM = 11
AD0EN = 1
Idle T C
Track T C
Idle
Track
TC
Idle..
T C Track..
T = Tracking
C = Converting
Figure 5.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4
Rev. 1.1
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