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C8051F54X_14 Datasheet, PDF (226/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family | |||
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C8051F54x
Table 22.1. SPI Slave Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode Timing* (See Figure 22.8 and Figure 22.9)
TMCKH
SCK High Time
1 x TSYSCLK
â
ns
TMCKL
SCK Low Time
1 x TSYSCLK
â
ns
TMIS
MISO Valid to SCK Shift Edge
1 x TSYSCLK + 20
â
ns
TMIH
SCK Shift Edge to MISO Change
0
â
ns
Slave Mode Timing* (See Figure 22.10 and Figure 22.11)
TSE
NSS Falling to First SCK Edge
2 x TSYSCLK
â
ns
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
â
ns
TSEZ
TSDZ
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
â
4 x TSYSCLK ns
â
4 x TSYSCLK ns
TCKH
SCK High Time
5 x TSYSCLK
â
ns
TCKL
TSIS
SCK Low Time
MOSI Valid to SCK Sample Edge
5 x TSYSCLK
2 x TSYSCLK
â
ns
â
ns
TSIH
SCK Sample Edge to MOSI Change
2 x TSYSCLK
â
ns
TSOH
TSLH
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change ï
(CKPHA = 1 ONLY)
â
6 x TSYSCLK
4 x TSYSCLK ns
8 x TSYSCLK ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
226
Rev. 1.1
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