C8051F54X_14 Datasheet, PDF (166/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.21. P2MDIN: Port 2 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF3; SFR Page = 0x0F
Bit
Name
Function
7:0 P2MDIN[7:0] Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P2MDOUT register.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
Note: P2.2-P2.7 are only available on the 32-pin packages.
SFR Definition 18.22. P2MDOUT: Port 2 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xA6; SFR Page = 0x0F
Bit
Name
Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Note: P2.2-P2.7 are only available on the 32-pin packages.
166
Rev. 1.1