C8051F54X_14 Datasheet, PDF (91/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
12.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SMBus Address Register (SFR “SMB0ADR”, located at
address 0xB9 on SFR Page 0x0F). The device is also using the SPI peripheral (SPI0) and the Programma-
ble Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control func-
tion in its interrupt service routine, and so its associated ISR is set to high priority. At this point, the SFR
page is set to access the SMB0ADR SFR (SFRPAGE = 0x0F). See Figure 12.2.
0x0F
(SMB0ADR)
SFR Page
Stack SFR's
SFRPAGE
SFRNEXT
SFRLAST
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SMB0ADR
While CIP-51 executes in-line code (writing a value to SMB0ADR in this example), the SPI0 Interrupt
occurs. The CIP-51 vectors to the SPI0 ISR and pushes the current SFR Page value (SFR Page 0x0F) into
SFRNEXT in the SFR Page Stack. The SFR page needed to access SPI0’s SFRs is then automatically
placed in the SFRPAGE register (SFR Page 0x00). SFRPAGE is considered the “top” of the SFR Page
Stack. Software can now access the SPI0 SFRs. Software may switch to any SFR Page by writing a new
value to the SFRPAGE register at any time during the SPI0 ISR to access SFRs that are not on SFR Page
0x00. See Figure 12.3.
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