C8051F54X_14 Datasheet, PDF (210/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 21.1. SCON0: Serial Port 0 Control
Bit
7
6
5
4
3
2
1
0
Name OVR0 PERR0 THRE0 REN0
TBX0
RBX0
TI0
RI0
Type R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
0
0
0
0
0
SFR Address = 0x98; Bit-Addressable; SFR Page = 0x00
Bit Name
Function
7 OVR0 Receive FIFO Overrun Flag.
0: Receive FIFO Overrun has not occurred
1: Receive FIFO Overrun has occurred; A received character has been discarded due
to a full FIFO.
6 PERR0 Parity Error Flag.
When parity is enabled, this bit indicates that a parity error has occurred. It is set to 1
when the parity of the oldest byte in the FIFO does not match the selected Parity Type.
0: Parity error has not occurred
1: Parity error has occurred.
This bit must be cleared by software.
5 THRE0 Transmit Holding Register Empty Flag.
0: Transmit Holding Register not Empty—do not write to SBUF0.
1: Transmit Holding Register Empty—it is safe to write to SBUF0.
4 REN0 Receive Enable.
This bit enables/disables the UART receiver. When disabled, bytes can still be read
from the receive FIFO.
0: UART1 reception disabled.
1: UART1 reception enabled.
3 TBX0 Extra Transmission Bit.
The logic level of this bit will be assigned to the extra transmission bit when XBE0 is set
to 1. This bit is not used when Parity is enabled.
2 RBX0 Extra Receive Bit.
RBX0 is assigned the value of the extra bit when XBE1 is set to 1. If XBE1 is cleared to
0, RBX1 will be assigned the logic level of the first stop bit. This bit is not valid when
Parity is enabled.
1
TI0 Transmit Interrupt Flag.
Set to a 1 by hardware after data has been transmitted, at the beginning of the STOP
bit. When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to
the UART0 interrupt service routine. This bit must be cleared manually by software.
0
RI0 Receive Interrupt Flag.
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by soft-ware. Note that RI0 will remain set to ‘1’ as long as there is
data still in the UART FIFO. After the last byte has been shifted from the FIFO to
SBUF0, RI0 can be cleared.
210
Rev. 1.1