C8051F54X_14 Datasheet, PDF (159/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.8. P2MASK: Port 2 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P2MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB2; SFR Page = 0x00
Bit
Name
Function
7:0 P2MASK[7:0] Port 2 Mask Value.
Selects P2 pins to be compared to the corresponding bits in P2MAT.
0: P2.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P2.n pin logic value is compared to P2MAT.n.
Note: Ports 2.2-P2.7 only available on 32-pin packages.
SFR Definition 18.9. P2MAT: Port 2 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P2MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xB1; SFR Page = 0x00
Bit
Name
Function
7:0 P2MAT[7:0] Port 2 Match Value.
Match comparison value used on Port 2 for bits in P2MAT which are set to 1.
0: P2.n pin logic value is compared with logic LOW.
1: P2.n pin logic value is compared with logic HIGH.
Note: Ports 2.2-P2.7 only available on 32-pin packages.
Rev. 1.1
159