C8051F54X_14 Datasheet, PDF (207/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
21.2. Data Format
UART0 has a number of available options for data formatting. Data transfers begin with a start bit (logic
low), followed by the data bits (sent LSB-first), a parity or extra bit (if selected), and end with one or two
stop bits (logic high). The data length is variable between 5 and 8 bits. A parity bit can be appended to the
data, and automatically generated and detected by hardware for even, odd, mark, or space parity. The stop
bit length is selectable between 1 and 2 bit times, and a multi-processor communication mode is available
for implementing networked UART buses. All of the data formatting options can be configured using the
SMOD0 register, shown in SFR Definition 21.2. Figure 21.2 shows the timing for a UART0 transaction
without parity or an extra bit enabled. Figure 21.3 shows the timing for a UART0 transaction with parity
enabled (PE0 = 1). Figure 21.4 is an example of a UART0 transaction when the extra bit is enabled
(XBE0 = 1). Note that the extra bit feature is not available when parity is enabled, and the second stop bit
is only an option for data lengths of 6, 7, or 8 bits.
MARK
SPACE
BIT TIMES
START
BIT
D0
D1
DN-2
DN-1
STOP
STOP
BIT 1
BIT 2
N bits; N = 5, 6, 7, or 8
Optional
(6,7,8 bit
Data)
Figure 21.2. UART0 Timing Without Parity or Extra Bit
MARK
SPACE
BIT TIMES
START
BIT
D0
D1
DN-2
DN-1
PARITY
STOP
STOP
BIT 1
BIT 2
N bits; N = 5, 6, 7, or 8
Figure 21.3. UART0 Timing With Parity
Optional
(6,7,8 bit
Data)
MARK
SPACE
BIT TIMES
START
BIT
D0
D1
DN-2
DN-1
EXTRA
STOP
STOP
BIT 1
BIT 2
N bits; N = 5, 6, 7, or 8
Figure 21.4. UART0 Timing With Extra Bit
Optional
(6,7,8 bit
Data)
Rev. 1.1
207