C8051F54X_14 Datasheet, PDF (251/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
IDLE
PCA0MD
CWW
I DD
DT L
LEC
K
CCCE
PPPC
SSSF
210
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
SYSCLK/12
000
SYSCLK/4
001
Timer 0 Overflow
010
ECI
011
SYSCLK
100
External Clock/8
101
PCA0L
read
Snapshot
Register
To SFR Bus
0
PCA0H
PCA0L
Overflow
To PCA Interrupt System
1
CF
To PCA Modules
Figure 24.2. PCA Counter/Timer Block Diagram
24.2. PCA0 Interrupt Sources
Figure 24.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be
used to generate a PCA0 interrupt. They are as follows: the main PCA counter overflow flag (CF), which is
set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on
an overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of
that module. These event flags are always set when the trigger condition occurs. Each of these flags can
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-
ting the EA bit and the EPCA0 bit to logic 1.
Rev. 1.1
251