C8051F54X_14 Datasheet, PDF (252/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
(for n = 0 to 2)
PCA0CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n n n F
6nnn
n
n
PCA Counter/Timer 8, 9,
10 or 11-bit Overflow
PCA Counter/Timer 16-
bit Overflow
PCA Module 0
(CCF0)
PCA0CN
CCCCCCCC
FRCCCCCC
FFFFFF
543210
PCA0MD
C WW
I DD
DT L
L EC
K
CCCE
PPPC
SSSF
210
ECCF0
0
1
0
1
PCA Module 1
(CCF1)
ECCF1
0
1
PCA Module 2
(CCF2)
ECCF2
0
1
PCA Module 3
(CCF3)
PCA Module 4
(CCF4)
PCA Module 5
(CCF5)
ECCF3
0
1
ECCF4
0
1
ECCF5
0
1
PCA0PWM
ACE
CC
ROC
LL
S VO
SS
EFV
EE
L
LL
10
0
1
Set 8, 9, 10, or 11 bit Operation
EPCA0
EA
0
1
0 ^Interrupt
Priority
1
Decoder
Figure 24.3. PCA Interrupt Block Diagram
24.3. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16-
Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the
CIP-51 system controller. These registers are used to exchange data with a module and configure the
module's mode of operation. Table 24.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM
registers used to select the PCA capture/compare module’s operating mode. All modules set to use 8, 9,
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a
PCA0CPMn register enables the module's CCFn interrupt.
252
Rev. 1.1