|
C8051F54X_14 Datasheet, PDF (273/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family | |||
|
◁ |
C8051F54x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
ï® Updated â2. Ordering Informationâ to include -A (Automotive) devices and automotive qualification
information.
ï® Updated Figure 4.6.
ï® Updated supply current related specifications throughout â6. Electrical Characteristicsâ .
ï® Updated SFR Definition 7.1 (REF0CN) to change VREF high setting to 2.20 V from 2.25 V.
ï® Updated Figure 8.1 to indicate that Comparators are powered from VIO and not VDDA.
ï® Updated the Gain Table in â5.3.1. Calculating the Gain Valueâ to fix the ADC0GNH Value in the last row.
ï® Updated Table 10.1 with correct timing for all branch instructions, MOVC, and CPL A.
ï® Updated Table 14.1 to indicate behavior when performing a Flash operation in reserved space.
ï® Updated â14.1. Programming the Flash Memoryâ to clarify behavior of 8-bit MOVX instructions and
when writing/erasing Flash.
ï® Updated SFR Definition 14.3 (FLSCL) to include FLEWT bit definition. This bit must be set before
writing or erasing Flash. Also updated Table 6.5 to reflect new Flash Write and Erase timing.
ï® Updated â16.7. Flash Error Resetâ with an additional cause of a Flash Error reset.
ï® Updated â18.1.3. Interfacing Port I/O in a Multi-Voltage Systemâ to remove note regarding interfacing to
voltages above VIO.
ï® Updated â20. SMBusâ to remove all hardware ACK features, including SMB0ADM and SMB0ADR
SFRs.
ï® Updated SFR Definition 21.1(SCON0) to correct SFR Page to 0x00 from All Pages.
ï® Updated CP Register Definition 24.2 with proper Device ID.
Note: All items from the C8051F54x Errata dated November 5th, 2009 are incorporated into this data sheet.
Revision 1.0 to Revision 1.1
ï® Updated â1. System Overviewâ with a voltage range specification for the internal oscillator.
ï® Updated Figure 5.4, â12-Bit ADC Burst Mode Example With Repeat Count Set to 4,â on page 33 with
new timing diagram when using CNVSTR pin.
ï® Updated Table 6.6, âInternal High-Frequency Oscillator Electrical Characteristics,â on page 53 with new
conditions for the internal oscillator accuracy. The internal oscillator accuracy is dependent on the
operating voltage range.
ï® Updated â6. Electrical Characteristicsâ to remove the internal oscillator curve across temperature
diagram.
ï® Updated SFR Definition 7.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
ï® Fixed incorrect cross references in â8. Comparatorsâ .
ï® Updated SFR Definition 9.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
ï® Updated Figure 11.2, âFlash Program Memory Map,â on page 86 with correct address for start of lock
byte page from 0x3900 to 0x3A00.
ï® Updated â15.3. Suspend Modeâ with note regarding ZTCEN.
ï® Added Port 2 Event and Port 3 Event to wake-up sources in â17.2.1. Internal Oscillator Suspend Modeâ
ï® Updated â19. Local Interconnect Network (LIN)â with a voltage range specification for the internal
oscillator.
ï® Updated LIN Register Definitions for LIN0MUL and LIN0DIV to correct the reset value.
ï® Updated C2 Register Definitions 25.2 and 25.3 with correct C2 and SFR addresses.
Rev. 1.1
273
|
▷ |