C8051F54X_14 Datasheet, PDF (212/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 21.3. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
Name
SBUF0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x99; SFR Page = 0x00
Bit Name
Function
7:0 SBUF0[7:0] Serial Data Buffer Bits 7–0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
SFR Definition 21.4. SBCON0: UART0 Baud Rate Generator Control
Bit
Name
Type
Reset
7
Reserved
R/W
0
6
SB0RUN
R/W
0
5
Reserved
R/W
0
4
Reserved
R/W
0
3
Reserved
R/W
0
2
Reserved
R/W
0
SFR Address = 0xAB; SFR Page = 0x0F
Bit Name
Function
7 Reserved Read = 0b; Must Write 0b;
6 SB0RUN _{Baud Rate Generator Enable.}
0: Baud Rate Generator disabled. UART0 will not function.
1: Baud Rate Generator enabled.
5:2 Reserved Read = 0000b; Must Write = 0000b;
1:0 SB0PS[1:0] _{Baud Rate Prescaler Select.}
00: Prescaler = 12.
01: Prescaler = 4.
10: Prescaler = 48.
11: Prescaler = 1.
1
0
SB0PS[1:0]
R/W
0
0
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Rev. 1.1