C8051F54X_14 Datasheet, PDF (49/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 6.2. Global Electrical Characteristics (Continued)
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
Parameter
Conditions
Min Typ Max
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
I_DD4
V_DD = 2.1 V, F = 200 kHz
— 50 —
V_DD = 2.1 V, F = 1.5 MHz
— 410 —
V_DD = 2.1 V, F = 25 MHz
— 6.5 8.0
V_DD = 2.1 V, F = 50 MHz
— 13 16
I_DD4
V_DD = 2.6 V, F = 200 kHz
— 67 —
V_DD = 2.6 V, F = 1.5 MHz
— 530 —
V_DD = 2.6 V, F = 25 MHz
— 8.0 15
V_DD = 2.6 V, F = 50 MHz
— 16 25
I_DD Supply Sensitivity⁴
F = 25 MHz
F = 1 MHz
— 55 —
— 58 —
I_DD Frequency Sensitivity ^{4.6 V}DD ^{= 2.1V, F < 12.5 MHz, T = 25 °C — 0.26 —}
V_DD = 2.1V, F > 12.5 MHz, T = 25 °C — 0.26 —
V_DD = 2.6V, F < 12.5 MHz, T = 25 °C — 0.34 —
V_DD = 2.6V, F > 12.5 MHz, T = 25 °C — 0.34 —
Digital Supply Current^4
(Stop or Suspend Mode)
Oscillator not running,
V_DD Monitor Disabled
Temp = 25 °C
Temp = 60 °C
Temp= 125 °C
—
1
—
—
6
—
— 70 —
Notes:
1. Given in Table 6.4 on page 52.
2. V_IO should not be lower than the V_DD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Guaranteed by characterization. Does not include oscillator supply current.
5. IDD estimation for different frequencies.
6. Idle IDD estimation for different frequencies.
Units
µA
µA
mA
mA
µA
µA
mA
mA
%/V
mA/MHz
µA
Rev. 1.1
49