C8051F54X_14 Datasheet, PDF (29/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
5. 12-Bit ADC (ADC0)
The ADC0 on the C8051F54x consists of an analog multiplexer (AMUX0) with 25/18 total input selections
and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold, pro-
grammable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0 sub-
system has a special Burst Mode which can automatically enable ADC0, capture and accumulate
samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data
conversion modes, and window detector are all configurable under software control via the Special Func-
tion Registers shows in Figure 5.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P3.7, the Temperature Sensor output, V_DD, or GND with respect to GND. The voltage reference for
ADC0 is selected as described in Section “6.2. Temperature Sensor” on page 60. ADC0 is enabled when
the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
ADC0MX
ADC0TK
ADC0CN
P2.2-P2.7, P3.0 available
on 32-pin packages
P0.0
P0.7
P1.0
P1.7
P2.0
28-to-1
AMUX0
Start
Conversion
SYSCLK
Burst Mode
Logic
Burst Mode
Oscillator
25 MHz Max
Selectable
Gain
P2.7
P3.0
VDD
Temp Sensor
GND
ADC0GNH ADC0GNL ADC0GNA
VDD
12-Bit
SAR
ADC
00
Start
01
Conversion
10
11
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Accumulator
ADC0LTH ADC0LTL
AD0WINT
Window
Compare
32 _Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.1
29