C8051F54X_14 Datasheet, PDF (151/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Port
P0
P1
P2
P3
Special
Function
Signals
P2.2-P2.7, P3.0 only
available on the 32-pin
packages
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
UART_TX
UART_RX
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX
Figure 18.3. Peripheral Availability on Port I/O Pins
Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); and similarly when the UART or LIN are selected, the Crossbar assigns both pins associ-
ated with the peripheral (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART
TX0 is always assigned to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contig-
uously after the prioritized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
As an example configuration, if SPI0 in 4-wire mode, and PCA0 Modules 0, 1, and 2 are enabled on the
crossbar with P0.1, P0.2, and P0.5 skipped, the registers should be set as follows: XBR0 = 0x04 (SPI0
enabled), XBR1 = 0x0C (PCA0 modules 0, 1, and 2 enabled), XBR2 = 0x40 (Crossbar enabled), and
P0SKIP = 0x26 (P0.1, P0.2, and P0.5 skipped). The resulting crossbar would look as shown in
Figure 18.4.
Rev. 1.1
151