C8051F54X_14 Datasheet, PDF (45/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 5.11. ADC0LTH: ADC0 Less-Than Data High Byte
Bit
7
6
5
4
3
2
1
0
Name
ADC0LTH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC6; SFR Page = 0x00
Bit
Name
Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 5.12. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit
7
6
5
4
3
2
1
0
Name
ADC0LTL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC5; SFR Page = 0x00
Bit
Name
Function
7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for right-justified data with
ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can
range from 0 to V_REF x (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer
value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0100 < ADC0H:ADC0L < 0x0200). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0100 or ADC0H:ADC0L > 0x0200). Figure 5.7 shows an exam-
ple using left-justified data with the same comparison values.
Rev. 1.1
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