C8051F54X_14 Datasheet, PDF (185/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
LIN Register Definition 19.9. LIN0DIV: LIN0 Divider Register
Bit
7
6
5
4
3
2
1
0
Name
DIVLSB[3:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
Indirect Address = 0x0C
Bit
Name
Function
7:0 DIVLSB LIN Baud Rate Divider Least Significant Bits.
The 8 least significant bits for the baud rate divider. The 9th and most significant bit
is the DIV9 bit (LIN0MUL.0). The valid range for the divider is 200 to 511.
LIN Register Definition 19.10. LIN0MUL: LIN0 Multiplier Register
Bit
7
6
5
4
3
2
1
0
Name
PRESCL[1:0]
LINMUL[4:0]
DIV9
Type
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Indirect Address = 0x0D
Bit
Name
Function
7:6 PRESCL[1:0] LIN Baud Rate Prescaler Bits.
These bits are the baud rate prescaler bits.
5:1 LINMUL[4:0] LIN Baud Rate Multiplier Bits.
These bits are the baud rate multiplier bits. These bits are not used in slave mode.
0
DIV9
LIN Baud Rate Divider Most Significant Bit.
The most significant bit of the baud rate divider. The 8 least significant bits are in
LIN0DIV. The valid range for the divider is 200 to 511.
Rev. 1.1
185