C8051F54X_14 Datasheet, PDF (244/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
T3MH
0
0
1
T3XCLK TMR3H Clock Source
0
SYSCLK/12
1
External Clock/8
X
SYSCLK
T3ML
0
0
1
T3XCLK TMR3L Clock Source
0
SYSCLK/12
1
External Clock/8
X
SYSCLK
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
T3XCLK
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR3
1
SYSCLK
TMR3RLH ^Reload
TCLK
TMR3H
TMR3RLL ^Reload
To SMBus
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
T3XCLK
Interrupt
1
TCLK _TMR3L
To ADC,
SMBus
0
Figure 23.8. Timer 3 8-Bit Mode Block Diagram
23.3.3. External Oscillator Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 3 can be
clocked from the system clock, or the system clock divided by 12, depending on the T3ML (CKCON.6),
and T3XCLK bits. When a capture event is generated, the contents of Timer 3 (TMR3H:TMR3L) are
loaded into the Timer 3 reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set. A capture event
is generated by the falling edge of the clock source being measured, which is the external oscillator/8. By
recording the difference between two successive timer capture values, the external oscillator frequency
can be determined with respect to the Timer 3 clock. The Timer 3 clock should be much faster than the
capture clock to achieve an accurate reading. Timer 3 should be in 16-bit auto-reload mode when using
Capture Mode.
If the SYSCLK is 24 MHz and the difference between two successive captures is 5861, then the external
clock frequency is as follows:
24 MHz/(5861/8) = 0.032754 MHz or 32.754 kHz
This mode allows software to determine the external oscillator frequency when an RC network or capacitor
is used to generate the clock source.
244
Rev. 1.1