C8051F54X_14 Datasheet, PDF (155/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
5
4
3
2
1
0
Name T1E
T0E
ECIE
PCA0ME[2:0]
SYSCKE Reserved
Type
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE2; SFR Page = 0x0F
Bit
Name
Function
7
T1E
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
6
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
5
ECIE PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
4:2 PCA0ME[2:0] PCA Module I/O Enable Bits.
000: All PCA I/O unavailable at Port pins.
001: CEX0 routed to Port pin.
010: CEX0, CEX1 routed to Port pins.
011: CEX0, CEX1, CEX2 routed to Port pins.
100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.
101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.
111: RESERVED
1 SYSCKE SYSCLK Output Enable.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
0 Reserved Always Write to 0.
Rev. 1.1
155