C8051F54X_14 Datasheet, PDF (177/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
19.7. LIN Registers
The following Special Function Registers (SFRs) and indirect registers are available for the LIN controller.
19.7.1. LIN Direct Access SFR Registers Definitions
SFR Definition 19.1. LIN0ADR: LIN0 Indirect Address Register
Bit
7
6
5
4
3
2
1
0
Name
LIN0ADR[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD3; SFR Page = 0x00
Bit
Name
Function
7:0 LIN0ADR[7:0] LIN Indirect Address Register Bits.
This register hold an 8-bit address used to indirectly access the LIN0 core registers.
Table 19.4 lists the LIN0 core registers and their indirect addresses. Reads and
writes to LIN0DAT will target the register indicated by the LIN0ADR bits.
SFR Definition 19.2. LIN0DAT: LIN0 Indirect Data Register
Bit
7
6
5
4
3
2
1
0
Name
LIN0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD2; SFR Page = 0x00
Bit
Name
Function
7:0 LIN0DAT[7:0] LIN Indirect Data Register Bits.
When this register is read, it will read the contents of the LIN0 core register pointed
to by LIN0ADR.
When this register is written, it will write the value to the LIN0 core register pointed
to by LIN0ADR.
Rev. 1.1
177