C8051F54X_14 Datasheet, PDF (128/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 15.1. PCON: Power Control
Bit
7
6
5
4
3
2
1
0
Name
GF[5:0]
STOP
IDLE
Type
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x87; SFR Page = All Pages
Bit Name
Function
7:2 GF[5:0] General Purpose Flags 5–0.
These are general purpose flags for use under software control.
1
STOP Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
0
IDLE Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
Serial Ports, and Analog Peripherals are still active.)
128
Rev. 1.1