C8051F54X_14 Datasheet, PDF (140/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
17.3. Clock Multiplier
The Clock Multiplier generates an output clock which is 4 times the input clock frequency scaled by a pro-
grammable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or 2/7. The Clock Multiplier’s input can be
selected from the external oscillator, or the internal or external oscillators divided by 2. This produces three
possible base outputs which can be scaled by a programmable factor: Internal Oscillator x 2, External
Oscillator x 2, or External Oscillator x 4. See Section 17.1 on page 135 for details on system clock selec-
tion.
The Clock Multiplier is configured via the CLKMUL register (SFR Definition 17.5). The procedure for con-
figuring and enabling the Clock Multiplier is as follows:
1. Reset the Multiplier by writing 0x00 to register CLKMUL.
2. Select the Multiplier input source via the MULSEL bits.
3. Select the Multiplier output scaling factor via the MULDIV bits
4. Enable the Multiplier with the MULEN bit (CLKMUL | = 0x80).
5. Delay for >5 µs.
6. Initialize the Multiplier with the MULINIT bit (CLKMUL | = 0xC0).
7. Poll for MULRDY > 1.
Important Note: When using an external oscillator as the input to the Clock Multiplier, the external source
must be enabled and stable before the Multiplier is initialized. See “17.4. External Oscillator Drive Circuit”
on page 142 for details on selecting an external oscillator source.
The Clock Multiplier allows faster operation of the CIP-51 core and is intended to generate an output fre-
quency between 25 and 50 MHz. The clock multiplier can also be used with slow input clocks. However, if
the clock is below the minimum Clock Multiplier input frequency (FCMmin), the generated clock will consist
of four fast pulses followed by a long delay until the next input clock rising edge. The average frequency of
the output is equal to 4x the input, but the instantaneous frequency may be faster. See Figure 17.2 below
for more information.
if F_CMin >= F_CMmin
F_{CM in}
F_{CM out}
if F_CMin < F_CMmin
F_{CM in}
F_{CM out}
Figure 17.2. Example Clock Multiplier Output
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Rev. 1.1