C8051F54X_14 Datasheet, PDF (241/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 23.9. TMR2RLL: Timer 2 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR2RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCA; SFR Page = 0x00
Bit
Name
Function
7:0 TMR2RLL[7:0] Timer 2 Reload Register Low Byte.
TMR2RLL holds the low byte of the reload value for Timer 2.
SFR Definition 23.10. TMR2RLH: Timer 2 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR2RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xCB; SFR Page = 0x00
Bit
Name
Function
7:0 TMR2RLH[7:0] Timer 2 Reload Register High Byte.
TMR2RLH holds the high byte of the reload value for Timer 2.
Rev. 1.1
241