C8051F54X_14 Datasheet, PDF (26/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Figure 4.4. QFN-32 Landing Diagram
Table 4.4. QFN-32 Landing Diagram Dimensions
Dimension
C1
C2
e
X1
Min
Max
4.80
4.90
4.80
4.90
0.50 BSC
0.20
0.30
Dimension
X2
Y1
Y2
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Min
3.20
0.75
3.20
Max
3.40
0.85
3.40
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3x3 array of 1.0 mm openings on a 1.20 mm pitch should be used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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Rev. 1.1