C8051F54X_14 Datasheet, PDF (154/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0
Bit
7
6
5
4
3
2
1
0
Name CP1AE CP1E CP0AE CP0E SMB0E SPI0E Reserved URT0E
Type R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xE1; SFR Page = 0x0F
Bit Name
Function
7 CP1AE Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
6 CP1E Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
5 CP0AE Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
4 CP0E Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
3 SMB0E SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
2 SPI0E SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
1 Reserved Always Write to 0.
0 URT0E UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
154
Rev. 1.1