C8051F54X_14 Datasheet, PDF (86/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
C8051F540/1/2/3
Reserved Area
Lock Byte
Lock Byte Page
0x3FFF
0x3C00
0x3BFF
0x3BFE
0x3A00
Flash Memory Space
(16 kB Flash Device)
C8051F544/5/6/7
Lock Byte
Lock Byte Page
Flash Memory Space
(8 kB Flash Device)
0x1FFF
0x1FFE
0x1E00
0x0000
Figure 11.2. Flash Program Memory Map
0x0000
11.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F54x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can be
re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used to read
Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access feature
provides a mechanism for the C8051F54x to update program code and use the program memory space for
non-volatile data storage. Refer to Section “14. Flash Memory” on page 117 for further details.
11.2. Data Memory
The C8051F54x devices include 1280 bytes of RAM data memory. 256 bytes of this memory is mapped
into the internal RAM space of the 8051. The other 1024 bytes of this memory is on-chip “external” mem-
ory. The data memory map is shown in Figure 11.1 for reference.
11.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 11.1 illustrates the data memory organization of the C8051F54x.
86
Rev. 1.1