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C8051F54X_14 Datasheet, PDF (77/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family
C8051F54x
Table 10.1. CIP-51 Instruction Set Summary
Mnemonic
Description
Bytes
Clock
Cycles
Arithmetic Operations
ADD A, Rn
Add register to A
1
1
ADD A, direct
Add direct byte to A
2
2
ADD A, @Ri
Add indirect RAM to A
1
2
ADD A, #data
Add immediate to A
2
2
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
Add register to A with carry
Add direct byte to A with carry
Add indirect RAM to A with carry
Add immediate to A with carry
Subtract register from A with borrow
1
1
2
2
1
2
2
2
1
1
SUBB A, direct
Subtract direct byte from A with borrow
2
2
SUBB A, @Ri
Subtract indirect RAM from A with borrow
1
2
SUBB A, #data
Subtract immediate from A with borrow
2
2
INC A
Increment A
1
1
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
Increment register
Increment direct byte
Increment indirect RAM
Decrement A
Decrement register
1
1
2
2
1
2
1
1
1
1
DEC direct
Decrement direct byte
2
2
DEC @Ri
Decrement indirect RAM
1
2
INC DPTR
Increment Data Pointer
1
1
MUL AB
Multiply A and B
1
4
DIV AB
DA A
Divide A by B
Decimal adjust A
1
8
1
1
Logical Operations
ANL A, Rn
ANL A, direct
AND Register to A
AND direct byte to A
1
1
2
2
ANL A, @Ri
AND indirect RAM to A
1
2
ANL A, #data
AND immediate to A
2
2
ANL direct, A
AND A to direct byte
2
2
ANL direct, #data
AND immediate to direct byte
3
3
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
OR Register to A
OR direct byte to A
OR indirect RAM to A
OR immediate to A
OR A to direct byte
1
1
2
2
1
2
2
2
2
2
ORL direct, #data
OR immediate to direct byte
3
3
XRL A, Rn
Exclusive-OR Register to A
1
1
XRL A, direct
Exclusive-OR direct byte to A
2
2
XRL A, @Ri
Exclusive-OR indirect RAM to A
1
2
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
Rev. 1.1
77