C8051F54X_14 Datasheet, PDF (247/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
SFR Definition 23.14. TMR3RLL: Timer 3 Reload Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR3RLL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x92; SFR Page = 0x00
Bit
Name
Function
7:0 TMR3RLL[7:0] Timer 3 Reload Register Low Byte.
TMR3RLL holds the low byte of the reload value for Timer 3.
SFR Definition 23.15. TMR3RLH: Timer 3 Reload Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR3RLH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0x93; SFR Page = 0x00
Bit
Name
Function
7:0 TMR3RLH[7:0] Timer 3 Reload Register High Byte.
TMR3RLH holds the high byte of the reload value for Timer 3.
Rev. 1.1
247