C8051F54X_14 Datasheet, PDF (130/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
16.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V_DD settles above
V_RST. A delay occurs before the device is released from reset; the delay decreases as the V_DD ramp time
increases (V_DD ramp time is defined as how fast V_DD ramps from 0 V to V_RST). Figure 16.2. plots the
power-on and V_DD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V_DD monitor is enabled following a
power-on reset.
VDD
2.70
2.55
V_RST
2.0
1.0
t
/RST
Logic HIGH
Logic LOW
T_PORDelay
Power-On
Reset
VDD
Monitor
Reset
Figure 16.2. Power-On and V_DD Monitor Reset Timing
16.2. Power-Fail Reset/V_DD Monitor
When a power-down transition or power irregularity causes V_DD to drop below V_RST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 16.2). When V_DD returns
to a level above V_RST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if V_DD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V_DD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V_DD monitor is disabled by code and a software reset is performed, the
V_DD monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V_DD
monitor must be enabled to the higher setting (VDMLVL = 1) and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the V_DD monitor is not enabled and
set to the high level, any erase or write performed on Flash memory will cause a Flash Error device
reset.
130
Rev. 1.1