C8051F54X_14 Datasheet, PDF (52/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 6.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
RST Output Low Voltage
VIO = 5 V; IOL = 70 µA
—
RST Input High Voltage
RST Input Low Voltage
0.7 x V_IO
—
RST Input Pullup Current
RST = 0.0 V, VIO = 5 V
—
V_DD RST Threshold (V_RST-LOW)
1.65
V_DD RST Threshold (V_RST-HIGH)
2.25
Missing Clock Detector Timeout Time from last system clock
rising edge to reset initiation
V_DD = 2.1 V
200
V_DD = 2.5 V
200
Reset Time Delay
Delay between release of
—
any reset source and code 
execution at location 0x0000
Minimum RST Low Time to 
6
Generate a System Reset
V_DD Monitor Turn-on Time
—
V_DD Monitor Supply Current
—
Typ
—
—
—
49
1.75
2.30
340
250
155
—
60
1
Max Units
40
mV
—
0.3 x V_IO
115
µA
1.80
V
2.45
V
µs
600
600
175
µs
—
µs
100
µs
2
µA
Table 6.5. Flash Electrical Characteristics
V_DD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Flash Size
C8051F540/1/2/3
16384¹
C8051F544/5/6/7
8192
Endurance
20 k
150 k
—
Retention
125 °C
10
—
—
Erase Cycle Time
25 MHz System Clock
28
30
45
Write Cycle Time
25 MHz System Clock
79
84
125
V_DD
Write/Erase Operations
V_RST-HIGH2
—
—
1. On the 16 kB Flash devices, 1024 bytes at addresses 0x3C00 to 0x3FFF are reserved.
2. See Table 6.4 for the V_RST-HIGH specification.
Units
Bytes
Erase/Write
Years
ms
µs
V
52
Rev. 1.1