C8051F54X_14 Datasheet, PDF (238/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
T2MH
0
0
1
T2XCLK TMR2H Clock Source
0
SYSCLK/12
1
External Clock/8
X
SYSCLK
T2ML
0
0
1
T2XCLK TMR2L Clock Source
0
SYSCLK/12
1
External Clock/8
X
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
T2XCLK
SYSCLK / 12
0
External Clock / 8
1
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR2
1
SYSCLK
TMR2RLH ^Reload
TCLK
TMR2H
TMR2RLL ^Reload
To SMBus
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
Interrupt
1
TCLK _TMR2L
To ADC,
SMBus
0
Figure 23.5. Timer 2 8-Bit Mode Block Diagram
23.2.3. External Oscillator Capture Mode
Capture Mode allows the external oscillator to be measured against the system clock. Timer 2 can be
clocked from the system clock, or the system clock divided by 12, depending on the T2ML (CKCON.4),
and T2XCLK bits. When a capture event is generated, the contents of Timer 2 (TMR2H:TMR2L) are
loaded into the Timer 2 reload registers (TMR2RLH:TMR2RLL) and the TF2H flag is set. A capture event
is generated by the falling edge of the clock source being measured, which is the external oscillator / 8. By
recording the difference between two successive timer capture values, the external oscillator frequency
can be determined with respect to the Timer 2 clock. The Timer 2 clock should be much faster than the
capture clock to achieve an accurate reading. Timer 2 should be in 16-bit auto-reload mode when using
Capture Mode.
For example, if T2ML = 1b and TF2CEN = 1b, Timer 2 will clock every SYSCLK and capture every external
clock divided by 8. If the SYSCLK is 24 MHz and the difference between two successive captures is 5984,
then the external clock frequency is as follows:
24 MHz/(5984/8) = 0.032086 MHz or 32.086 kHz
238
Rev. 1.1