C8051F54X_14 Datasheet, PDF (181/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
LIN Register Definition 19.5. LIN0CTRL: LIN0 Control Register
Bit
7
6
5
4
3
2
1
0
Name STOP SLEEP TXRX DTACK RSTINT RSTERR WUPREQ STREQ
Type
W
R/W
R/W
R/W
W
W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Indirect Address = 0x08
Bit
Name
Function
7
STOP Stop Communication Processing Bit. (slave mode only)
This bit always reads as 0.
0: No effect.
1: Block the processing of LIN communications until the next SYNC BREAK signal.
6
SLEEP Sleep Mode Bit. (slave mode only)
0: Wake the device after receiving a Wakeup interrupt.
1: Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle
timeout.
5
TXRX Transmit / Receive Selection Bit.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
4
DTACK Data Acknowledge Bit. (slave mode only)
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit
will automatically be cleared to 0 by the LIN controller.
3
RSTINT Reset Interrupt Bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
2 RSTERR Reset Error Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
1 WUPREQ Wakeup Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automati-
cally be cleared to 0 by the LIN controller.
0
STREQ Start Request Bit. (master mode only)
1: Start a LIN transmission. This should be set only after loading the identifier, data
length and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
Rev. 1.1
181