C8051F54X_14 Datasheet, PDF (78/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 10.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic
Description
Bytes
Clock
Cycles
XRL A, #data
Exclusive-OR immediate to A
2
2
XRL direct, A
Exclusive-OR A to direct byte
2
2
XRL direct, #data
Exclusive-OR immediate to direct byte
3
3
CLR A
Clear A
1
1
CPL A
RL A
RLC A
RR A
RRC A
Complement A
Rotate A left
Rotate A left through Carry
Rotate A right
Rotate A right through Carry
1
1
1
1
1
1
1
1
1
1
SWAP A
Swap nibbles of A
1
1
Data Transfer
MOV A, Rn
Move Register to A
1
1
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
Move direct byte to A
Move indirect RAM to A
Move immediate to A
Move A to Register
Move direct byte to Register
2
2
1
2
2
2
1
1
2
2
MOV Rn, #data
Move immediate to Register
2
2
MOV direct, A
Move A to direct byte
2
2
MOV direct, Rn
Move Register to direct byte
2
2
MOV direct, direct
Move direct byte to direct byte
3
3
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
Move indirect RAM to direct byte
Move immediate to direct byte
Move A to indirect RAM
Move direct byte to indirect RAM
Move immediate to indirect RAM
2
2
3
3
1
2
2
2
2
2
MOV DPTR, #data16
Load DPTR with 16-bit constant
3
3
MOVC A, @A+DPTR
Move code byte relative DPTR to A
1
3
MOVC A, @A+PC
Move code byte relative PC to A
1
3
MOVX A, @Ri
Move external data (8-bit address) to A
1
3
MOVX @Ri, A
Move A to external data (8-bit address)
1
3
MOVX A, @DPTR
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
Move external data (16-bit address) to A
Move A to external data (16-bit address)
Push direct byte onto stack
Pop direct byte from stack
Exchange Register with A
1
3
1
3
2
2
2
2
1
1
XCH A, direct
Exchange direct byte with A
2
2
XCH A, @Ri
Exchange indirect RAM with A
1
2
XCHD A, @Ri
Exchange low nibble of indirect RAM with A
1
2
Boolean Manipulation
CLR C
CLR bit
Clear Carry
Clear direct bit
1
1
2
2
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
78
Rev. 1.1