C8051F54X_14 Datasheet, PDF (174/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
Table 19.3. Autobaud Parameters Examples
System Clock (MHz) Prescaler Divider
25
24.5
24
22.1184
16
12.25
1
312
1
306
1
300
1
276
1
200
0
306
12
11.0592
8
0
300
0
276
0
200
19.3. LIN Master Mode Operation
The master node is responsible for the scheduling of messages and sends the header of each frame con-
taining the SYNCH BREAK FIELD, SYNCH FIELD, and IDENTIFIER FIELD. The steps to schedule a mes-
sage transmission or reception are listed below.
1. Load the 6-bit Identifier into the LIN0ID register.
2. Load the data length into the LIN0SIZE register. Set the value to the number of data bytes or "1111b" if
the data length should be decoded from the identifier. Also, set the checksum type, classic or
enhanced, in the same LIN0SIZE register.
3. Set the data direction by setting the TXRX bit (LIN0CTRL.5). Set the bit to 1 to perform a master
transmit operation, or set the bit to 0 to perform a master receive operation.
4. If performing a master transmit operation, load the data bytes to transmit into the data buffer (LIN0DT1
to LIN0DT8).
5. Set the STREQ bit (LIN0CTRL.0) to start the message transfer. The LIN controller will schedule the
message frame and request an interrupt if the message transfer is successfully completed or if an error
has occurred.
This code segment shows the procedure to schedule a message in a transmission operation:
LIN0ADR
LIN0DAT
LIN0ADR
LIN0DAT
LIN0ADR
LIN0DAT
= 0x08;
// Point to LIN0CTRL
|= 0x20;
// Select to transmit data
= 0x0E;
// Point to LIN0ID
= 0x11;
// Load the ID, in this example 0x11
= 0x0B;
// Point to LIN0SIZE
= ( LIN0DAT & 0xF0 ) | 0x08;
// Load the size with 8
LIN0ADR = 0x00;
// Point to Data buffer first byte
for (i=0; i<8; i++)
{
LIN0DAT = i + 0x41;
// Load the buffer with ‘A’, ‘B’, ...
LIN0ADR++;
// Increment the address to the next buffer
}
LIN0ADR = 0x08;
// Point to LIN0CTRL
LIN0DAT = 0x01;
// Start Request
The application should perform the following steps when an interrupt is requested.
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Rev. 1.1