C8051F54X_14 Datasheet, PDF (137/275 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F54x
17.2. Programmable Internal Oscillator
All C8051F54x devices include a programmable internal high-frequency oscillator that defaults as the sys-
tem clock after a system reset. The internal oscillator period can be adjusted via the OSCICRS and OSCI-
FIN registers defined in SFR Definition 17.3 and SFR Definition 17.4. On C8051F54x devices, OSCICRS
and OSCIFIN are factory calibrated to obtain a 24 MHz base frequency. Note that the system clock may be
derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64, or 128, as defined by the
IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
17.2.1. Internal Oscillator Suspend Mode
When software writes a logic 1 to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the sys-
tem clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped
until one of the following events occur:
 Port 0 Match Event.
 Port 1 Match Event.
 Port 2 Match Event.
 Port 3 Match Event.
 Comparator 0 enabled and output is logic 0.
When one of the oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals
resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes
execution at the instruction following the write to SUSPEND.
Note: When entering suspend mode, firmware must set the ZTCEN bit in REF0CN (SFR Definition 7.1).
Rev. 1.1
137